| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_44bd4af8e23d007348830d2f65360e88 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-938
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-932
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-76 |
| filingDate |
2005-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99d3ead7b24b293be08f1f1ce38b3a36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed3a3186be8c1d747fee88791512308c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe323edc5f4fc90c1e314834532ec915
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b8ce284d733b29b3e1a5133a27b620f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d5dffe715f8b1c546c325ebcae3944e |
| publicationDate |
2007-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CA-2589432-A1 |
| titleOfInvention |
Method, system, and apparatus for gating configurations and improved contacts in nanowire-based electronic devices |
| abstract |
Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core. |
| priorityDate |
2004-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |