http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2447204-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_42ad7c7647a24745759a9ee1d56e480e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1044 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-29 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-095 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-29 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M13-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2003-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2010-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e56d58520e51be0b964dac894c5192c7 |
| publicationDate | 2010-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2447204-C |
| titleOfInvention | Error correction scheme for memory |
| abstract | An embedded DRAM ECC architecture for purging data errors is disclosed. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation in order to identify parity failure for the word. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus. A method for initializing the memory upon power up in order to prepare the memory for writing data, and methods and circuits for generating the corresponding row and column parity bits during a write operation are also disclosed. |
| priorityDate | 2002-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 38.