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filingDate 2001-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2011-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_76ce2b06adf1a6822a3d5b2e50483488
publicationDate 2011-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-2404270-C
titleOfInvention Three dimensional device integration method and integrated device
abstract A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device (14) having a substrate (20) to an element (10) and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semi-conductor device. Interconnections (51) may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices (165) to an element (163), and the element may have recesses (167) in which the semiconductor devices are disposed. A conductor array (78) having a plurality of contact structures may be formed on an exposed surface of the semiconductor device (77), vias may be formed through the semiconductor device to device regions, and interconnection (81, 82, 83) may be formed between said device regions and said contact structures.
priorityDate 2000-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 51.