http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2317993-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4ddcb273a108a5d8472b335280098e06 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-14 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-18 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-18 |
| filingDate | 2000-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3d3c293d54a0b838535987392cf6b481 |
| publicationDate | 2001-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2317993-A1 |
| titleOfInvention | Arrangement for clock supply of high bit rate switching network structures |
| abstract | Arrangement for Clock Supply of High Bit Rate Switching Network Structures The invention is directed to on arrangement for clock supply of high bit-rate switching network structures in a digital narrow band switching system such as EWSD. A clock frequency signal (CLK2) traditionally generated with a crystal-controlled oscillator (11) as well as a corresponding frame clock signal (FMR2) are converted into low-voltage CMOS level signals and supplied to a system PL1 (2) for high frequencies. This contains a discretely constructed VCO 6 with a sine oscillator that derives a higher-frequency signal from the supplied clock signal and converts this into a high-frequency clocks signal (CLK92) of the output side. A feedback signal derived in this part serves as input-side feedback signal for a phase detector (8) in low-voltage CMOS technology. The feedback signal as well as the output-side high-frequency signal (CLK92) also serve for phase decoupling of the input-side frame clock signal (FMB2) from the output-side frame clock signal (FMB92) and for the phase-coupling thereof to the output-side high-frequency signal (CLK92). The input-side clock signals (CLK92, PMR92) arc distributed in pairs via a clock distribution system (3) dimensioned within narrow tolerances and are supplied to respective application-specific or, respectively, customized ~Cs (4) in low-voltage CMOS technology. This division onto various stages and onto components of different technologies in low-voltage technology allow the dimensioning and configuration with cost beneficial component. |
| priorityDate | 1999-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.