http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2294471-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_65d70bbe0b849898693723beabc90c00 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S331-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-095 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-099 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-1806 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-113 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-095 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-099 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-113 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-18 |
| filingDate | 1998-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2002-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5acfb1e4c01f8128932a8e0b07824485 |
| publicationDate | 2002-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2294471-C |
| titleOfInvention | Method and arrangement for locking in a yig-tuned oscillator |
| abstract | The object of the invention is to provide a lock-in process and device for a YIG-tuned oscillator which takes into account ageing and hysteresis of the YIG-tuned oscillator. This object is attained in that during a predetermined frequency change, the frequency of the YIG-tuned oscillator (1) is preset by means of a microprocessor (17) that progressively changes the current (ISP) in the main tuning coil (13) of the YIG-tuned oscillator (1) by an iterative capture routine, until the capture range (.DELTA.FM) of the switched-on frequency-locked loop, which changes with the coil current (ISP), includes the new operating frequency (fSET). The switched-on frequency-locked loop then pulls the oscillator frequency into the capture range of the PLL and the PLL locks-in the oscillator frequency to the new operating frequency (fSET). The microprocessor (17) interrupts the capture routine when a PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (fSET) has been successfully locked-in. The invention is used in a process for locking-in a phase-locked loop (PLL) to a YIG-tuned oscillator whose frequency is brought into the PLL capture range by a frequency-locked loop equipped with a frequency discriminator. When the PLL is locked-in, the frequency-locked loop can be switched off. |
| priorityDate | 1997-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.