http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2284772-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b105432e26388793d9735fb4aad9a383 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3013 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3001 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-345 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-345 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F5-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-00 |
| filingDate | 1998-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2011-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b83ad00e90dfba8b8f9fd34e0413c64 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a18b85841884068572639633862ea010 |
| publicationDate | 2011-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2284772-C |
| titleOfInvention | Computer processor and method for data streaming |
| abstract | A processor having a modified Harvard architecture having first and second memories (224 X, Y), an address register file divided into first and second sets of registers (216 X, Y), first and second stream registers (226 X, Y), and a general purpose register file (218) for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmatic logic unit (ALU, 230) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction. |
| priorityDate | 1997-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
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|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/protein/ACCQ07295 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID415821907 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID122034 |
Total number of triples: 26.