http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2240616-C

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filingDate 1998-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2002-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b3990b889dbb0526749f9a305906c784
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publicationDate 2002-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-2240616-C
titleOfInvention Cache address generation
abstract A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. The cache array is accessed by multiplexing two most-recently-used (MRU) arrays which are addressed and accessed substantially in parallel with effective address generation, the outputs of which MRU arrays are generated, one by assuming a carryin of zero, and the other by assuming a carryin of one to the least significant bit of the portion of the effective addressed used to access the MRU arrays. The hit rate in the MRU array is improved by hashing within an adder the adder's input operands with predetermined additional operand bits.
priorityDate 1997-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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