http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2220993-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_47e68b4e3399502a8f6a30d8b5e4bf87 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16968b522cba0e73048a694a6a5538a http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_034ba49409402cd7121cc265f80f0cfa http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_29e58031c948ceb4865d18e8596be447 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8015 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 |
| filingDate | 1997-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_339baac34ee15ab6e24023fcbcc39f9f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb8aa9bcda5db946919343f30a99bc9d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d17d50c43b4442aca461df993dfc2de http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1da17c918b5f8ecfa0d49c82a4c0dcd |
| publicationDate | 1999-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2220993-A1 |
| titleOfInvention | Single-instruction-multiple-data processor |
| abstract | A single-instruction multiple-data array processor optimised for both linear andnon-linear signal processing is disclosed. The array processor includes processing elements each with three data input ports, three data output ports, a processing unit, and output selection unit, two comparators, and a selection control unit. The processing elements are capable of providing several data values at each of several output ports and in so doing, support execution of non-linear operations such as sort within a single instruction execution cycle. The processor is also provided with two shift register channels for flexible data organization concurrent with data processing. The two shift register channels are complemented by an inter-processing element communication channel. In use, the comparators set flags for controlling selection of a data value to provide to each of the output ports. |
| priorityDate | 1997-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.