http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2171170-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_61155939891010276932bda73b832c00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-374 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-368 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-374 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 |
| filingDate | 1996-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4b95198bc1c3bd4564f76396525b743 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fea3d72ca628b5f7abe445d39d1c8fb8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3961d0a9c444138fbcfbbcbc4d7165c3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d3c65de7abaeb6881f239ee2d84d4901 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c83264943487cc98f2119e6cac931ec3 |
| publicationDate | 1996-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2171170-A1 |
| titleOfInvention | Pipelined distributed bus arbitration system |
| abstract | The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration occurs within all the respective bus arbiters occurs in a second clock cycle. |
| priorityDate | 1995-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.