http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2112136-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a7f1d2de15fa55f50c792fac17861388 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2012-5681 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2012-5651 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2012-5678 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-455 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-1553 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L12-5601 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04Q11-0478 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L49-108 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L12-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04Q3-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04Q3-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04Q11-04 |
| filingDate | 1992-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1999-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3395578b3478fc5df8d3a2983760d19b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_922f22bd35291a647e48726e3cd6ae36 |
| publicationDate | 1999-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2112136-C |
| titleOfInvention | Broadband input buffered atm switch |
| abstract | Broadband ATM switches for switching ATM packetized data in timeslots are disclo sed In one embodiment, the switch includes input buffer means, a space switch for connecting input ports and outpu t ports at successive timeslots and a system scheduler. The timeslot utilization processing is carried out by using a contain ed addressable memory. A bit map is provided for registering the timeslot utilization of the input ports and the output ports. An encoder means determines the earliest commonly available timeslot for connecting input ports and their requested output ports. There is further disclosed an architecture in which groups of input ports share common buffer memories and in which the system sched uler processes grouped inputs, thus taking advantage of the architecture's similar characteristics and advantages to those of the common memory switch. |
| priorityDate | 1991-10-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.