http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2058092-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5cb907719b87723dfcacf23516cbb0b5 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-167 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-167 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-38 |
| filingDate | 1991-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_860432ab37d2cd3989481aad2fc04b55 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8b423bafc3c63d195cbccba7cd709587 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_24e7513816ce40a2b09e9038e48e003e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bc7d45d5182debb6e3ab60942de6cee1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_91aba913db195097907dcf0f8482a522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f030422d360af2f6c83eceeb5dcc87b2 |
| publicationDate | 1992-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2058092-A1 |
| titleOfInvention | Circuit device for interfacing between several processing units equipped with microprocessors |
| abstract | A B S T R A C T CIRCUIT DEVICE FOR INTERFACING BETWEEN SEVERAL PROCESSING UNITS EQUIPPED WITH MICROPROCESSORS The invention is directed to the field of control electro-nic devices and in particular relates to a circuit device for interfacing between several processing units equipped with micro-processors which consist essentially of a control unit (2) con-nected to serial ports and to parallel ports (3,4,6,7), and a memory (4) relative to the control circuit and an interface (9) for a RAM memory (10), in such a way as, when two different processors are connected through such device, it is possible make the processors to operate, even if of different structure, by exploiting said RAM memory as a connection element, usable in a fashion type multiplexed multiport and/or of type circular queue, FIFO, LIFO; said RAM memory i.e appears configurable at will, depending on processors to be interfaced. M.Fucito - M.Recchia 1/4 (combined) |
| priorityDate | 1990-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.