| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9f0549460cc527d48437953332d89e40 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03G11-006 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03G11-00 |
| filingDate |
1991-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e2a94f2fb3e4fc4258b90453ea9aef7d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f737a237d560f7d0994cd86140eadf9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f262918eea5ece58492b6c5fa2af39b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_579677c9741178d0d88507e57680f812
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_442b658cf448f0efad377c14ac713883 |
| publicationDate |
1991-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CA-2038227-A1 |
| titleOfInvention |
Field effect transistor limiting device |
| abstract |
SHORT: Field effect transistor limiting device. The invention relates to a transistor effect limiter device. field, the bias circuit of which consists of two power supplies at constant voltage: one on the grid (Vgs) the other on the drain (Vds), a resistive load (Rg) being arranged in series with supply to the gate of this transistor (10). Application in particular to the field of space telecommunications. FIGURE TO PUBLISH: Fig. 1 |
| priorityDate |
1990-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |