http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2028043-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_107927219457ae0abab813f9639a0934 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01C7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01C17-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01C17-006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01C1-142 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C3-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C17-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C17-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C1-142 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C13-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01C17-28 |
| filingDate | 1990-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1999-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0517f6ab2eecaf8ad102ac358955a228 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c69c25a5ffb303d55088c784731ac7d8 |
| publicationDate | 1999-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2028043-C |
| titleOfInvention | Chip form of surface mounted electrical resistance and its manufacturing method |
| abstract | The chip form electrical resistance is designed to be soldered notably on a printed circuit card or on an hybrid circuit substratum. It includes an electrically insulating substratum (1) of the ceramic type, to which is attached by mean of a layer of adhesive organic resin (2) a sheet of metal or of resistive alloy (3). The layer of resin (6) leaves in the area of the two opposite sides of the substratum (1), two free areas (5), at the extremities of the cut-up resistive sheet (3). These two parts (5) of the resistive sheet are each covered by a thin layer (8) of a metal or alloy adhering to the resistive sheet (3), this layer (8) being covered by a second thicker layer (9) of metal or conductive alloy, and this second layer (9) being covered by a third, also thicker layer (14) of a solderable metal, these three layers superimposed (8, 9, 14) spreading equally over both lateral sides opposite the substratum (1) and partially on its face (13) opposite the cut-up resistive sheet (3). To be used notably in printed or hybrid circuits. |
| priorityDate | 1989-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.