http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2016683-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6d44b4d59a56381632fd5e6c1c95749f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0886 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-0886 |
| filingDate | 1990-05-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_753918788d6857232361580839cfe9c1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7d4564f02c885a72ee18092c3fb297bb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f520344f7395710e3d6ca5fe456dc287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_622218e8bcf7ca886fc66df06662386d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9f67b70a73fc523aee03049119fa01d7 |
| publicationDate | 1990-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2016683-A1 |
| titleOfInvention | Quadruple word, multiplexed, paged mode and cache memory |
| abstract | QUADRUPLE WORD, MULTIPLEXED, PAGED MODE AND CACHE MEMORY Abstract of the Disclosure A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance. |
| priorityDate | 1989-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.