http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2016252-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_02660742d97aafc1000d2a855884da59 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3861 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate | 1990-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_49d78788ec64dde1eab85ab3d5db2f2f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ae295913805fa2dca087f3346352ce7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9dae029bbbd2191b4dd20ed7224c42eb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fade988c26b7bd3f48e9a64fccb10a5 |
| publicationDate | 1990-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2016252-A1 |
| titleOfInvention | Paired instruction processor precise exception handling mechanism |
| abstract | PAIRED INSTRUCTION PROCESSOR PRECISE EXCEPTION HANDLING MECHANISM ABSTRACT OF THE DISCLOSURE A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized. |
| priorityDate | 1989-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.