http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2007051-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e08fd85d97265d6c31ab40f372843d81 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8069 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8076 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78 |
| filingDate | 1990-01-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1994-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4dc4fa8f70c693ee7a8a76f9103d5b9d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f93d5ac335feb131b99448fd70c63adb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca41bf85dc7061260dd72b049f9e797b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_031cfb35c361bdaf1371831874db02cf http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3abe3c9befba9c2012d5a5f3fc0e4050 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a8b2d0bb08b0a993dca49f56b40d683 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5aa50c507ddd13b222131545142edc6f |
| publicationDate | 1994-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2007051-C |
| titleOfInvention | Signal processor |
| abstract | SIGNAL PROCESSOR ABSTRACT A signal processor (10) comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor (10) comprises an external interface (11) having a serial control port and a plurality of bidirectional parallel ports. The interface (11) transfers control and data signals between the signal processor (10) and external devices. The parallel ports are configurable as individual parallel ports or as coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller (17) comprising a micropro-gram memory (18) and a control program memory (15) is coupled to the interface (11) which loads applications programs into the control program memory (15) and executes the programs. The arithmetic element controller (17) controls the process-ing of control and data signals in the signal processor (10). A plurality of pipelined arithmetic elements are coupled to the arithmetic element controller each comprising a data store memory (13) a multiplier (114) and a register and arithmetic logic unit (20). Each arithmetic element has its data store memory (13) coupled to the external interface (11) to receive and store data signals and to its multiplier (14) and the reg-ister and arithmetic logic unit (20) in order to perform fixed and floating point arith-metic operations on the data stored in the data store memory (13). These arithmetic operations are performed in accordance with application program and microprograminstructions contained in the control program and the microprogram memories. Thepresent invention provides for a high performance architecture for use with vector and matrix signal processing algorithms that minimizes the amount of hardware needed to implement them. |
| priorityDate | 1989-01-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.