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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
filingDate 1989-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1993-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34feaaedc35eab66ba57e2b786dc5f4a
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publicationDate 1993-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-1314631-C
titleOfInvention Process for fabricating integrated circuits having shallow junctions
abstract Abstract For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 µm and aremade through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completesthe contact.
priorityDate 1988-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 32.