http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1310762-C

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36
filingDate 1991-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1992-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75abb92a9b124e193c07d838f92f3020
publicationDate 1992-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-1310762-C
titleOfInvention Arbitration technique for a split transaction bus in a multiprocessor computer system
abstract ARBITRATION TECHNIQUE FOR A SPLIT TRANSACTION BUS IN A MULTIPROCESSOR COMPUTER SYSTEM Abstract of the Disclosure An arbitration technique for a split transaction bus of a computer system obtains higher data throughput as a result of giving responders (e.g. memories) absolute pri-ority over initiators (e.g. processors and I/O adapters), as a result of assigning all responders a higher priority than any initiator. Precedence is also given to retrying initiators which failed to complete a transaction because the module to which the transfer was addressed was busy. the requests from non-retrying initiators are temporarily rescinded to give precedence to the requests from retrying initiators. There is an absolute limit or bound to the number of requests which a retrying module may make before it is granted mastership of the bus to accomplish its transfer. To accomplish test and set and memory scrub transactions with a minimum time loss, the bus of the computer system creates a null conductivity cycle immediately following the cycle in which the address of the memory location to be tested and set or scrubbed is transferred.
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priorityDate 1986-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 20.