| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7484dfb88aa1e069ce6111b4d3245bac |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2236 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G10L15-285
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-7832 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-267 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G10L15-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G10L15-14 |
| filingDate |
1988-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1991-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd3e1f7b9350106351bec739f6f45ea4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e8820257ebca4d2514684f926705f884
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_482d7d5f71c1b49a50e77efe0de1040f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5e5d5b39a70adbf0dc2e0d07648802a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e53f12cd6575b1e1399bbf4627fac1ed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b3970de3d2e3de1ed4497818b11faf4 |
| publicationDate |
1991-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CA-1286778-C |
| titleOfInvention |
Integrated processing unit, particularly for connected speech recognition systems |
| abstract |
Abstract In a two-level hierarchical system for connected speech recognition, wherein the lower level consists of one or more processing units, the circuit which constitutes one of the aforementioned units also provides for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but accessed in uniform manner by the internal addressing unit. |
| priorityDate |
1987-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |