http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1274587-A
Outgoing Links
Predicate | Object |
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e08fd85d97265d6c31ab40f372843d81 |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R25-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03D13-004 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03D13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-089 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R25-00 |
filingDate | 1986-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 1990-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_031d4360722c3ecbe12811efea7e8778 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0da5cd636858205a37f0ddd8da8abd5a |
publicationDate | 1990-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | CA-1274587-A |
titleOfInvention | Digital phase-frequency discriminator comprising simplified reset means and associated method |
abstract | DIGITAL PHASE-FREQUENCY DISCRIMINATOR COMPRISING SIMPLIFIED RESET MEANS AND ASSOCIATED METHOD ABSTRACT OF THE DISCLOSURE The present invention provides a phase-frequency discriminator comprising a first RS latch coupled to provide first output signals, said first RS latch including an S input terminal coupled to receive first input signals; a second RS latch coupled to provide second output signals, said second RS latch including an S input terminal coupled to receive second input signals; a third RS latch including an S input terminal coupled to a ? output terminal of said first RS latch and including a ? output terminal coupled to an R input terminal of said first RS latch; a fourth RS latch including an S input terminal coupled to a ? output terminal of said second RS latch and including a ? output terminal coupled to an R input terminal of said second RS latch; and reset means for providing a reset signal when said first and second input signals both have changed from a first to a second logical state such that the first and second output signals change back from the second to the first logical state after a reset time interval substantially long enough for the respective first and second output signals to reach full logic amplitude levels for the second logical state. |
priorityDate | 1985-11-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.