http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1245373-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate | 1987-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1988-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9ba8d9393206100d5792e60f224ab98 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3036d3c0f0d08d59583869a4e591b62e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_069e1121d204c62bd850a909b06bc6f7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30ecb1cd4760867b3a6c6087d14ee8ff |
| publicationDate | 1988-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1245373-A |
| titleOfInvention | Sidewall spacers for cmos circuit stress relief/isolation and method for making |
| abstract | Abstract Sidewall Spacers For CMOS Circuit Stress Relief Isolation And Method For Making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical. |
| priorityDate | 1986-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.