http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1214884-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cceefacdcbabc92106fb8048d91a893d |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0817 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-084 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-00 |
| filingDate | 1984-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1986-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_57d3910964f70b154e8023e6044fd115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b1dae8bf35d98ed7262bb0a87f371a3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b79805e7c54826b265cc8d7f6db17d7e |
| publicationDate | 1986-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1214884-A |
| titleOfInvention | Computer hierarchy control |
| abstract | A B S T R A C T A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor. |
| priorityDate | 1983-07-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.