http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1213325-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8e6a13e4ae501eb40decf5732cf09c6 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-27 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 |
| filingDate | 1984-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1986-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_094e8da2ecd4e423b72657915cbd2ae7 |
| publicationDate | 1986-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1213325-A |
| titleOfInvention | Digital circuit testing arrangement |
| abstract | ABSTRACT DIGITAL CIRCUIT TESTING ARRANGEMENT In order to test a digital circuit, such as a digital logic circuit 100, for faults, during the first three cycles of a test operation of many cycles in duration, a predetermined input word is delivered to the input terminals of the logic circuit. Throughout the remaining cycles of the test operation, each output terminal of the circuit is connected by an input multiplexer 200 to a fixed different one (or more) of the input terminals, whereby output of each cycle serves as input for the next cycle of the test operation. A counter 300 counts the number of test operation cycles and sends an enabling signal to s signature detector 400 when the counter counts a predetermined number of test cycles. Finally, in response to this enabling signal, each output terminal's output bit developed during the last cycle of the test operation is compared by the signature detector 400 with the corresponding "correct" bit. Any discrepancy between any such output bit and the corresponding expected fault-free bit indicates at least one fault in the circuit. |
| priorityDate | 1983-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 66.