http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1188405-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d2051317369a779747701bc0ebe411a4
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-04126
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K17-60
filingDate 1982-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1985-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b77a0020c591e014f17f88c66d75013f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0ad6f4a08b3796f3ec10c3cd94e8b32c
publicationDate 1985-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-1188405-A
titleOfInvention Translating circuit for television receiver on-screen graphics display signals
abstract Abstract of the Disclosure A DC coupled signal translating circuit for supplying auxiliary graphics information switching signals to a video signal processor. The switching signal comprises plural switching levels including a quiescent level. The translating circuit includes first and second complementary conductivity input transistors with interconnected emitter signal inputs for receiving switching currents representa-tive of the graphics switching signals via a conductor which undesirably exhibits a parasitic capacitance. The transistors are biased to conduct a nominal quiescent current and develop collector output currents which are proportional to the input switching currents, and which are respectively coupled via current repeating networks to control inputs of the video processor. Switching delays attributable to the parasitic capacitances of the input coupling conductor are significantly reduced due to the emitter voltage clamping action of the input transistors for all conditions of the input switching signals.
priorityDate 1981-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 23.