http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1184248-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4f45ecc4568ed2971b4df5867be5856 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-50 |
| filingDate | 1982-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1985-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8cd44c6c59513b1f0ef9681f3a9b4fb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f295310ce62d05aa1e9bad5617913ac |
| publicationDate | 1985-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1184248-A |
| titleOfInvention | Semiconductor memory cell margin test circuit |
| abstract | SEMICONDUCTOR MEMORY CELL MARGIN TEST CIRCUIT ABSTRACT OF THE DISCLOSURE A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (Vcc*) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (Vcc*) is the semiconductor memory circuit main supply source (Vcc) in normal operation but can be forced to a different voltage during the margin test. |
| priorityDate | 1981-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.