http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1182578-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_cceefacdcbabc92106fb8048d91a893d |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-32 |
| filingDate | 1982-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1985-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f33feede81a85a780696b02a08d0c5f6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d9438ab4ebb282d2c0404a890e69dec http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f911f1e27a79756d4badc6ea76c706c |
| publicationDate | 1985-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1182578-A |
| titleOfInvention | Pause apparatus for a memory controller with interleaved queuing apparatus |
| abstract | ABSTRACT OF THE DISCLOSURE A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstand-ing the amount of bus delay incurred in transmitting their memory requests. |
| priorityDate | 1981-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.