http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1170363-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4f45ecc4568ed2971b4df5867be5856 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-35606 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4023 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356086 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-402 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34 |
| filingDate | 1981-01-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1984-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fef7483f1ded077cc505a698cffeb12 |
| publicationDate | 1984-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1170363-A |
| titleOfInvention | Mos memory cell |
| abstract | MOS MEMORY CELL ABSTRACT OF THE DISCLOSURE An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (20) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (20) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (K) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K). |
| priorityDate | 1980-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578835 |
Total number of triples: 25.