http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1150855-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2b8b744d430e252fa21c14c2b8dee176 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66954 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-321 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-339 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-321 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
| filingDate | 1980-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1983-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4c107352c15c146a1011d8a8f2859d9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_44651a47c7b67914b58099950a676274 |
| publicationDate | 1983-07-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1150855-A |
| titleOfInvention | Method of manufacturing a semiconductor device |
| abstract | ABSTRACT: A method of manufacturing a semiconductor device in which a surface of a semiconductor body is provided with a first insulating layer having a dielec-tric thickness which is homogeneous throughout the surface, on which a first conductor pattern of poly-crystalline silicon is provided, on which first con-ductor pattern a second insulating layer is formed by oxidation of said pattern in such manner that the dielectric thickness of the first insulating layer remains approximately constant, after which a second conductor pattern is provided on and beside the second insulating layer, characterized in that insulating paths are formed between the formation of the second insulating layer and the provision of the second con-ductor pattern while avoiding an alignment step and while using successive depositing and etching steps, which insulating paths fill substantially only spaces below edges of the second insulating layer, during which deposition step a temporary layer is deposited to a thickness exceeding half the height of the space and during which etching step the temporary layer is removed from the second insulating layer. |
| priorityDate | 1979-10-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.