| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e9ec95f75bc5dcc8f2c6f36fd3ee1ca6 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-35 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-339
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
1978-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1982-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8279abff20f7040bfccd0504157cd66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb09f3e2d9d9d611b2584844bf2d4af0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31db4d159d11a4304517200c6d554ea2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a586a216fcb9c04de850ff41cc90977d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1242bf41cdd207f51b22fba98f916dfc |
| publicationDate |
1982-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CA-1129550-A |
| titleOfInvention |
Mos dynamic memory in a diffusion current limited semiconductor structure |
| abstract |
- 1 - J. T. Clemens 1-1-7-3-1 MOS DYNAMIC MEMORY IN A DIFFUSION CURRENT LIMITED SEMICONDUCTOR STRUCTURE Abstract of the Disclosure In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer of a layered structure. The semiconductor layer is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics. |
| priorityDate |
1977-11-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |