http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-1115421-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-504 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-494 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-508 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-504 |
| filingDate | 1979-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1981-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a73dbe1d491f16a991888d2df8f39c2 |
| publicationDate | 1981-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-1115421-A |
| titleOfInvention | Digital adder |
| abstract | A DIGITAL ADDER Abstract of the Disclosure A digital adder comprises at least two, first and second 1-bit adders; first and second carry circuits which store therein output signals of carry output terminals of said first and second adders and apply them to carry input terminals of said first and second adders, respectively, in response to a predetermined clock signal; first input means for applying each pair of a plurality of pairs of data to be added up and each consisting of a predetermined number of bits, to said first adder in 1-bit sequence from least significant bits of said each pair of data in response to said clock signal; second input means for applying the data to be added to the carry signal delivered from said first adder by the addition of most significant bits of said each pair of data, to said second adder in 1-bit sequence from the least significant bits in response to said clock signal and upon termination of the application of said pair of data to said first adder; a first gate circuit which inhibits the carry signal delivered from said first adder by the addition of the most significant bits of said each pair of data, from being applied to said first carry circuit and applies said carry signal to said second carry circuit; and means for combining outputs of said first and second adders so as to attach the output of said second adder onto a more significant bit side of the output of said first adder and for delivering the combined output as one data. |
| priorityDate | 1978-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 54.