| abstract |
the present invention relates to a high peak bandwidth I / O channel embedded in a multilayer surface interface that forms a bus circuit electrically interfacing an input or output port on a first semiconductor array with an input or output port on a second semiconductor array, where the high peak bandwidth I / O channel includes pathways in electrical communication with the input and output ports on the first and second semiconductor arrays, a connection channel comprising a conductive medium embedded within a low permittivity / ultra low loss dielectric that electrically interconnects the pathways, a passive network filtering circuit comprising capacitive, inductive, and resistive elements incorporated with the I / O channel width high-peak band, a multi-layer surface interface comprising the channel connection embedded in a data signal plane, a conduit medium additional ive to form power plans and ground plans, or optional signal control plans; where, the passive network filter circuit comprises components that include a high energy density electroceramic dielectric that polarizes and depolarizes with femto-second response times. |