http://rdf.ncbi.nlm.nih.gov/pubchem/patent/AU-2021107091-A4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9716896e137dc5df52d7d00499752dc7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_534c53ad962b4de87de9ba0ed0c3a141 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_606c98c52f820735cd150fea93f8bc5c |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7839 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82Y10-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2021-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f7b23e01d59ae83c1718c0789ee95d1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d2df9ed298a2fce621ffdecb9b5a56d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb450cd00f1de2cbd58cb0df3528b524 |
| publicationDate | 2021-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | AU-2021107091-A4 |
| titleOfInvention | Ans/d spacer engineered dg-ambipolar fet devicefor investigating the thermal dependence of the dc, analog and rf performance |
| abstract | The present invention generally relates to a S/D spacer engineered nDG-Ambipolar FET device. The device comprisesa source and a drain ncontacts, sandwiching a lightly p-doped nanowire channel are made of nNiSi2 ; a gate-channel and a spacer-channel underlap, to improve an onncurrent and on-off current ratio of the device; a gate dielectric constant, nabove the lightly p-doped nanowire channel, when increased for a fixed nequivalent oxide thickness improves its delay performance; a control gate ninjects a desired carrier type into the lightly p-doped nanowire channel to nmake the device behave as either a n or p-FET; and a polarity gate blocks nan injection of an alternate carriers wherein the drain and the polarity ngate are kept fixed at a positive bias for n-type operation and the control ngate is swept from negative to positive values which initiates downward nmovement of band edges.nNrq no w Ti n4 EE nuJ I? nap m nd 00 nR 0q qn~ ~ O N W!VO t no ~ ,S~1WYSI n0 a- or ncr. u nI Ni IC¶ nN nit7 o 'F7 n(A)zu Nienwo nIN |
| priorityDate | 2021-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5461123 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559541 |
Total number of triples: 24.